1. Field of the Invention
The present invention relates to a method of fabricating a bit line structure, and particularly to a method of fabricating a narrow bit line structure.
2. Description of the Prior Art
Recently, ultra large scale integration (ULSI) semiconductor technologies have dramatically increased the integrated circuit density on the chips formed on the semiconductor substrate. This increase in circuit density has resulted from downsizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching, and other semiconductor technology innovations. However, future requirements for even greater circuit density is putting additional demand on the semiconductor processing technologies and on device electrical requirements.
The rapidly increasing integrated circuit in the number of cells on the DRAM chip, it is becoming increasingly difficult to fabricate a narrow bit line structure. FIGS. 1A and 1B shows the cross-sectional view of a traditional bit line structure 160. At first, the polysilicon layer 120 is formed on the interpoly dielectric layer 110 and the landing pad 100. Afterwards, the tungsten silicide layer 130 is formed on the polysilicon layer 120. Next, the silicon-oxy-nitride layer 140 is formed on the tungsten silicide layer 130. Finally, the defined photoresist layer 150 is formed, having a width about 0.2 .mu.m, as shown in FIG. 1A. However, a portion of silicon-oxy-nitride layer 140, a portion of the tungsten silicide layer 130, and a portion of the polysilicon layer 120 are etched to expose the land pad 100 and the interpoly dielectric layer 110, using the defined photoresist layer 150 as a mask. Then, the defined photoresist layer 150 is removed on silicon-oxy-nitride layer 140. Finally, the bit line structure 160 is formed on the landing pad 100, as shown in FIG. 1B. Due to this bit line structure 160 will not obtain the linewidth of 0.1 .mu.m. Thus, this present invention is disclosed by applying novel processes, and improving the disadvantage.